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![]() USB
![]() Isochronous test patch
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| Author | Topic: Isochronous test patch |
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Tsuneo Member |
Isochronous test patch This test patch demonstrates the isochronous transfer on 'F32x. But don't expect much for the moment. Only the transfer protocol was replaced to isochronous on USB_INT_Cypress in this patch. After implementing the vendor request, USB_ADC is planned. This test program is based on USB_BULK_Cypress and USB_INT_Cypress. Please refer "USB_INT and USB_BULK on Cypress device driver" USB_ISO_TEST (modified USB_INT_Cypress) Device driver This is the last message before my vacation. I'll be off until next Monday.. Bye!! Tsuneo PS My USB topics [This message has been edited by Tsuneo (edited November 05, 2005).] IP: Logged |
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Javier New Member |
I am working with Iso-Transfer and this working well. Wanted to know as I can optimize the data transfer?. In case of having 64 ready data to send them to the PC, and soon to return to count without lost. At the moment I have working I modulate to 64 bytes by package. IP: Logged |
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Tsuneo Member |
Hi Javier, This test code is simply made to clear several points about isochronous on 'F32x. I'm now coding continuous transfer with the endpoint3 to get 256000 byte/sec bandwidth as I promised to you about 2 weeks ago. I hope I can finish it this week end ![]() Tsuneo IP: Logged |
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Javier New Member |
Thanks Mr. Tsuneo I am working strong with test ISO, to obtain a transference of my data to the PC, without lost. I am optimizing my codes to obtain it. If you develop the code to transmit 256 kbytes/s with Endpoint 3 would be very good and I would like to see that speed. Thanks to help us since it does. IP: Logged |
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Javier New Member |
Hello. I am handling Iso Transfer, with packages of 64 bytes. With converter ADC of the F320 receipt signals of 10kHz and they see well when I make the graph, but if handling signals of smaller frequency these are seen very badly, they seem stairs with great steps (signals of 100 Hertz). I believe that this happens because there is a time that is lost when the data are being transmitted USB way. I believe that it is necessary to handle a block of memory for this, but since it could do it? if it is not thus, then as can be the solution to be able to transmit data in all the frequencies up to 10 kHz.? IP: Logged |
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Tsuneo Member |
Hi Javier, a) Firmware: I'm now working on direct FIFO writing method. In this method, the ADC data is directly pushed into the FIFO without buffering every time the ADC ends conversion. And when the FIFO becomes full, INPRDY bit is set to send the packet. Both method, bufferd or direct, will result full or empty packet if the transfer rate is faster than the data rate produced by sampling. USB engine sends empty (zero-length) packet if the FIFO is not ready when Isochronous IN transaction occurs. Double buffering is necessary for these schema. Direct FIFO method has the advantage on speed and memory usage. However, the weak point of this method is that FIFO access is spread out everywhere. As both FIFO access and USB operation, such as vendor request, use USB registers, they interfere mutually. I believe FIFO access method should be improved if SiLabs plans a revised version of USB MCU. b) Host application: Anyway, the dificulty on Isochronous lies on Host application than firmware to get high bandwidth continuously. I spend almost all of my spare time to poke about the host application these days. Tsuneo [This message has been edited by Tsuneo (edited September 09, 2004).] IP: Logged |
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Javier New Member |
In this message I cannot see my question, nor the answer that occurred the same one are messages 4 and 5 of Isochronous test patch IP: Logged |
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