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  F340 - Timer

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Author Topic:   F340 - Timer
hafblud
Member 		posted August 22, 2010 10:03 AM     Click Here to See the Profile for hafblud   Click Here to Email hafblud     Edit/Delete Message
Hi
I want to create some delay using timer0. I did following mathematics.

SYSCLK : 12 Mhz
SYSCLK / 48 : 12/48 x10e6
Time for 1 Cycle (48 / SYSCLK)= 4 us
Time for FFFF cycles = 4e-6 * 0xFFFF
= 262 mS
Is this delay achievable with timer0?

If i am making a mistake here please guide me to the right calculations.

regards
hafblud

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erikm
Member 		posted August 22, 2010 12:04 PM     Click Here to See the Profile for erikm   Click Here to Email erikm     Edit/Delete Message
where does '48' come from?

Erik

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hafblud
Member 		posted August 22, 2010 01:32 PM     Click Here to See the Profile for hafblud   Click Here to Email hafblud     Edit/Delete Message
CKCON: Clock Control

Bit2: T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.

Bits1–0: SCA1-SCA0: Timer 0/1 Prescale Bits.
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.

SCA1 SCA0 Prescaled Clock
0 0 System clock divided by 12
0 1 System clock divided by 4
1 0 System clock divided by 48
1 1 External clock divided by 8

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