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![]() ADC/DAC/VREF/Comparators
![]() 12-Bit ADC conversion flikers heavily on C8051F500?
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| Author | Topic: 12-Bit ADC conversion flikers heavily on C8051F500? |
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dingyg99 Member |
Dear all: We are using the C8051F500 to finished ADC and send it to the master node via CAN bus, now we found the ADC conversion flikers heavily, why? In our board, there are two DC voltage which values to be 4.989V and 4.364V by multimeter, and the difference is 4.989V-4.364V=0.625V, we have taken long time monitor on the two voltage, they keep very steady. We then assign the P0.2 and P0.3 to acquire the value two voltage, it is found the ADC result flikers heavily. To get a smoother value, we put them in data pool(item size=200) for averge. V1 = ADC: P0.2 [This message has been edited by dingyg99 (edited August 05, 2010).] IP: Logged |
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dingyg99 Member |
Below is the ADC init code: // ***************************************************************************** // Switch to active page // The regulator output=2.6V // The voltage reference=VDD // Enable the ADC0 // Restore the sfr page [This message has been edited by dingyg99 (edited August 05, 2010).] IP: Logged |
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dingyg99 Member |
Below is the ADC data acquision code: // ***************************************************************************** // Backup the sfr page // Switch to active page // Get the repeat counter // The repeat counter case 0X01: case 0X02: case 0X03: default: // The ADC channel // All the conversion // Restore the sfr page // Regulate the value // 12-bit ADC results // The final result // ***************************************************************************** // The ADC convert result // Return the value IP: Logged |
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tony.hague Member |
I would get rid off all the stuff to do with repeat counters which apperears not to be used; there are a couple of bugs in it (setting the busy flag to start a convert then waiting for not busy usually fails, and you have 0x16 where you mean 16). Your issues are most likely electrical, I would guess. I've plotted your data above and it doesn't look outrageous. Note particlarly that the analog inputs must NEVER exceed VIO (looks like you are close) and that a little analog filtering on the input usually yeilds rewards. If you are using VDD as the reference, this is likely to provide a noise path too. Make sure it is well decoupled, or use the internal reference (noting that it must be routed out to a pin and decoupled if you do). IP: Logged |
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vanmierlo Member |
It's better to wait for AD0INT instead of !AD0BUSY. IP: Logged |
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dingyg99 Member |
Dear Tony: I have tried according to your instructions to add a 0.1uF capacitor on the ADC channels, then the ADC result improved a lot. In this example we mount 8 client nodes on the CAN bus, the master node receive the data via the CAN bus and print out by the UART0 port. Please note that I have fixed the bug you pointed out in the function GetADC0Value16 (0X10 misspelling to 0X16), although it does not affect the ADC result. Below is sample of the ADC result: #0X01 Reading ADC0 ... OK V1=4.912 V2=4.362 V3=0.632 V4=4.964 V5=4.344 V6=0.620 V7=0.003 #0X01 Reading ADC0 ... OK V1=4.973 V2=4.380 V3=0.607 V4=4.965 V5=4.345 V6=0.620 V7=0.016 #0X01 Reading ADC0 ... OK V1=4.912 V2=4.362 V3=0.636 V4=4.965 V5=4.345 V6=0.621 V7=0.005 #0X01 Reading ADC0 ... OK V1=4.940 V2=4.383 V3=0.611 V4=4.964 V5=4.344 V6=0.620 V7=0.020 #0X01 Reading ADC0 ... OK V1=4.912 V2=4.362 V3=0.636 V4=4.964 V5=4.344 V6=0.620 V7=0.011 #0X01 Reading ADC0 ... OK V1=4.990 V2=4.370 V3=0.611 V4=4.964 V5=4.345 V6=0.619 V7=0.004 #0X01 Reading ADC0 ... OK V1=4.903 V2=4.380 V3=0.623 V4=4.964 V5=4.344 V6=0.620 V7=0.012 #0X01 Reading ADC0 ... OK V1=5.006 V2=4.333 V3=0.640 V4=4.964 V5=4.344 V6=0.621 V7=0.007 #0X01 Reading ADC0 ... OK V1=4.928 V2=4.383 V3=0.603 V4=4.965 V5=4.345 V6=0.620 V7=0.019 #0X01 Reading ADC0 ... OK V1=4.936 V2=4.350 V3=0.640 V4=4.965 V5=4.344 V6=0.620 V7=0.007 #0X01 Reading ADC0 ... OK V1=4.953 V2=4.387 V3=0.599 V4=4.964 V5=4.344 V6=0.620 V7=0.024 #0X01 Reading ADC0 ... OK V1=4.912 V2=4.383 V3=0.611 V4=4.963 V5=4.343 V6=0.620 V7=0.012 #0X01 Reading ADC0 ... OK V1=4.944 V2=4.387 V3=0.599 V4=4.964 V5=4.344 V6=0.620 V7=0.020 #0X01 Reading ADC0 ... OK V1=4.973 V2=4.354 V3=0.640 V4=4.964 V5=4.344 V6=0.620 V7=0.004 #0X01 Reading ADC0 ... OK V1=4.953 V2=4.383 V3=0.607 V4=4.964 V5=4.344 V6=0.620 V7=0.019 #0X01 Reading ADC0 ... OK V1=4.953 V2=4.354 V3=0.640 V4=4.964 V5=4.344 V6=0.620 V7=0.014 #0X01 Reading ADC0 ... OK V1=4.938 V2=4.383 V3=0.603 V4=4.964 V5=4.344 V6=0.620 V7=0.020 IP: Logged |
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dingyg99 Member |
Dear tony: We have tried to use the VREF as the ADC reference, we want to know if we use the VREF=1.50V/2.2V as the reference, the ADC perfomance may be improved or not. But to our supprise, the VREF output on P0.0 is not steady but changes heavily. for example: (2) Set REF0CN=0X11, the VREF=P0.1 should be 2.2V. but in most time the value maybe 2.023V, 1.845V, 0.379V etc. Although we occasionly watched the value to be steadly 2.233V. Please note that there is a 4.7uF + 0.1uF capacitor on this pin, the XBR initialization code is below: // ***************************************************************************** Then what cause the internal reference output on P0.0 not steady? Thanks & Best Regards IP: Logged |
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dingyg99 Member |
Dear All: To improve the ADC result, we may want to try the external voltage reference for the 12-bit ADC. We have select the ADI voltage REF195 (SO-8), does anyone used the exteranl reference? May the external reference improve the ADC performance? Thanks & Best Regards! [This message has been edited by dingyg99 (edited August 05, 2010).] IP: Logged |
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tony.hague Member |
VDDA and Analog ground connected properly ? IP: Logged |
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erikm Member |
VDDA and Analog ground connected properly ? reminds me of a fun episode. Prior to my arrival it had been decided that a given component was not "good enough" and another, more expensive, had been substituted with total success. I had a look and put a wire on the original board and it worked. the reason for the "total success" was not the new component but the new layout. many forget that "a wire is not a wire" in the high precision A/D game design is 10%, layout is 90% Erik [This message has been edited by erikm (edited August 06, 2010).] IP: Logged |
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