The maximum voltage is (AV+ - 300mV). Voltages higher than this will result in a gain error.

Regards,

Hmmmm. That would explain the symptoms I'm seeing here. But why can't I find this spec in the data sheet?

I have a design that uses either an F020/F120, in which AV+, VREF, VREF0, VREF2, VREFD are all linked together in hardware to +3.3V (too late to change now, units in the field).

Yes, I am seeing a gain error of about +6%. So now how to fix this? Prefferably in software only as I can do updates with bootloader. I could look at using the DAC for ADC reference voltage, or maybe I should just scale my ADC result by -6% and be done with it?

Because you're not looking right? It's mentioned in table 9.1 in both datasheets for F020/F120.

If you're lucky it's only a gain error, but I expect you'll also see non-linear behaviour.

On "Devices keep dying" topic, Joe experienced that devices were damaged by applying AV+ to VREF on 'F022, whose maximum input voltage of VREF is (AV+)-0.3 V.

I read the thread suggesting devices are damaged when connecting AV+ to VREF. In my case I appear to have been lucky, perhaps because I have RFBE = 0 (ref buffer off). Running for a considerable time now on both F020 and F120 devices with no failures. ADC result is approx +6% high (varies a little between devices), linearity appears ok but I haven't checked it thoroughly. (I did check the basic error against temperature variations and it's actually surprisingly good, approx +/-0.04% from "can of freeze" to "hot air gun" on the chip).

But I will have to fix my mistake in hardware. In this design I have AV+ and my analog sources connected to +3.3V analog rail. Easiest solution will probably be to create a new VREF of say 1.65V using a resistor divider from AV+, and drop the PGA gain from 1 to 0.5.