Better approach is,
The firmware has two tasks, one for measurement and logging to RAM cache, another for writing from the RAM cache to the external memory. Both tasks work concurrently.

Usually these external memory has 512 bytes / sector as the unit of single write. Therefore, when you choose RAM cache size as one of multiple of 512 bytes (ie. 512, 1024, ...), you'll get better speed performance as a whole.

Here is an excerpt from a SD card manual.

SanDisk SD Card Product Manual (ProductManualSDCardv2.2final.pdf)
2.5 System Performance
- Block Read Access Time: 0.5 ms (typ), 100 ms (max)
- Block Write Access Time: 0.5 ms (typ), 250 ms (max)

Usually, you can read from /write to SD card very quickly. But in the worst case, Write takes 250 ms. Design should be based on the worst case.

> This means I would need to plan for an XRAM of 20*512 = 10KB ?

No. You don't count in that MMC / SD / CF are block I/O device.
The outline of the process flow is as follows.

1) Just when the data logging starts, your firmware puts a header block (start time, sampling interval, etc) to the RAM cache on the on-chip XRAM.

2) A timer triggers ADC for sampling. The ADC completion ISR appends the ADC data to the header on the RAM cache. Every time ADC completes, the ISR appends data to the RAM cache. At the end of the cache, the write position returns to the head (ring buffer).

3) On the main loop, another task polls the cache size on the RAM. When it goes more than SD sector size, this task writes out one sector (or two) from cache to the SD card.

For two ADC channels, the ADC part should be more elaborated. But the outline of the code flow is same as above.

The RAM cache size is determined by the ADC data size, sampling rate and the Block Write Access Time (worst case) of SD card.

For example,
ADC data size: 4 bytes (2ch)
Sampling rate: 1 ms
SD sector size: 512 bytes
SD Block Write Access Time: 250 ms max

In the worst case, ADC generates 4 x 250 / 1 bytes while the firmware writes to the SD card. RAM cache should hold twice of this size, at least.

(4 * 250 / 1) * 2 = 2000 bytes
2048 bytes of RAM cache fits well.

To keep the throughput even in the worst case, you need to write 2 sectors (1024 bytes) at a time using multi-sector write.

Tsuneo