function CP220x_HW_Reset() returns CAL_ERROR.

What does it mean? Where I can find error codes for this functions?

Likely soldering problem, but check it in order.

1) Code modification on SiLabs TCP/IP stack for CP2201EK is found in this post.
http://www.cygnal.org/ubb/Forum1/HTML/001691.html
You may add another modification for ports, for your board configuration.
If you would want confirmation, post your schematic and initialization code.

Anyway, it's better to check the soldering of CP2201 pins.

2) Next, run an example code and check the CP2201 status.
Connect SiLabs IDE to your board over a debug adapter.
Just after CP220x_HW_Reset(), put a break point.
When the execution stops at the break point, read out CP2201 registers over IDE debug function.

a) RSTSTA: Reset Source Status Register
'View' menu > Debug Windows > CP2200 > BasicExtRegs.ini Registers
usually, it's value is 0x01

b) MAC address (written in factory)
'View' menu > Debug Windows > CP2200 > Indirect Memory > FLASH
6 byte MAC address starts at 0x1FFA on the 8K bytes FLASH
00-0B-3C-00-xx-xx

If you can't read out CP2201 registers and FLASH, you have trouble on the bus connection between the 'F340 and CP2201.

But it is very strange. I change CP2201 chip on first my pcb and create second pcb.
But trouble is on both boards.

I check all wires on pcb. It is similar to CP2201EK.

<..>
#if(BOARD == CP2201EB)
sbit AB4_RST = P3^6;
#else
sbit AB4_RST = P1^0;
#endif
<..>

void PORT_Init (void)
{
IT01CF =0x67;
XBR1 = 0x40;

P0MDOUT = 0x3F;
P1MDOUT |= 0xC8;
P2MDOUT = 0xFF;
P3MDOUT = 0xFF;

P2 &= ~0x80;
P2 |= 0x40;

P3MDOUT &= ~0x40;
P3 &= ~0x40;

// Set EMIF pins to push pull
P3MDOUT |= 0x80;
P4MDOUT |= 0xFF;
}

<..>

void EMIF_Init (void)
{
#if(BOARD == CP2201EB)
EMI0CF = 0x09;
#else
EMI0CF = 0x1B;
#endif

In my board, reset pin is P3^6 instead of P0^6 ( pinconfig and reset functions was changed accordingly to P3^6 )

When this code run, P3^6 is oscillate:

do {
temp_char = INT0RD;

if(timeout_expired()){
//return CAL_ERROR;
}

} while(1);

Therefore reset signal was setting then F340 read CP2201 registers.

Then I cut P3^6 reset wire from F340. Registers read correct

I see.
The code sets the EMIF multiplexed / split mode with bank select, as I posted on above link. In this setting, Port3 is assigned to high byte of external address bus, while the firmware accesses to the CP2201. In this period, the port3 value comes from EMI0CN, which is assigned to BASE_ADDRESS in the EMIF initialization.

mn_userconst.h
// The C8051F340 has 4K of on-chip XRAM. Off-chip access begins at 0x1000.
// Load EMI0CN with 0x10.
#define  BASE_ADDRESS   0x10

As the BASE_ADDRESS is 0x10, P3.6 is reset to low while the firmware accesses to the CP2201.

While the external bus is in idle, Port3 is kept in "parking" value, ie. P3 latch value. As the default, P3 latch value is 0xFF. P3.6 goes high in idle.

In this way, the "oscillation" is observed. You'll see this "oscillation" on other Port3 pins, too.

> Then I cut P3^6 reset wire from F340.

It's better to keep the reset function for error recovery.
To set up P3.6 for the CP2201 reset pin,
- Change EMIF mode to multiplexed / split mode without bank select
- Keep CP2201 #CS pin low (active).

EMI0CF = 0x05; // multiplexed / split mode without bank select
P3 = 0x7F;     // keep CP2201 #CS (P3.7) to low.

This modification makes other Port3 pins available, too.
You are connecting LCD pins to Port3.

Tsuneo